In FIG. 1, there is shown a prior art FPGA architecture, such as the ACTEL-1010(manufactured by ACTEL Corporation of Sunnyvale, Calif.). This is an 8-input logic module 11 for performing combinational logic functions. The logic module 11 comprises first and second multiplexers 10, and 12, having 3 inputs each and one output each. The outputs of the multiplexers 10, and 12 are connected to two inputs of a third multiplexer 14. The seventh and eighth inputs to the logic module 11 are coupled to a select input of multiplexer 14 through an gate 16. In Fig., there is shown the prior art Actel-1280 FPGA. This logic module 13 is slightly different than the Actel-1010. The select inputs of the first and second multiplexers 10 and 12 are coupled together and the third and fourth inputs to the logic module 13 are coupled to these select inputs through an AND gate. For a more detailed description of the prior art FPGA logic modules, See "Application Specific Logic Module Architecture for FPGAs", IEEE 1992 Custom Integrated Circuits Conference, by M. Agarwala et al.
It is an object of the present invention to provide an FPGA logic module which provides the same number of inputs and comparable layout area as the prior art.
It is a further object of the present invention to provide an FPGA logic module having comparable timing performance while having increased functionality over the prior art.
These and other objects of the invention will become apparent to those of ordinary skill in the art having reference to the following specification, in conjunction with the drawings.